Significant advances in silicon densities have allowed for the integration of many functions onto a single silicon chip. With this increased density, many of the peripherals in a computer system that were normally attached to the processor via an external bus now are attached via a local bus. In addition, the bandwidth requirements of these local buses are increasing due to the integration of various audio, video, and graphic functions along with the processor. As a result, achieving maximum local bus performance in its communications with processor cores and peripherals is a concern. This concern is particularly great when multiple devices in the computer system is linked to the same local bus.
FIG. 1A illustrates a conventional system 100 with a chip 110 containing a local bus 120. In this particular example, the local bus is the PowerPC 4XX Local Bus or "PLB" 120. However, other types of local buses may be used. The local bus 120 supports read and write data transfers between master and slave devices equipped with a local bus interface. A "master" device is one which requests access to or control of the local bus 120 and transmits and receives data across the local bus 120. A "slave" device is one which transmits or receives data across the local bus 120 and is responsive to a master. The slave may not request access to or control of the local bus 120.
FIG. 1B illustrates in more detail the connection between master 20 and 22 and slaves 26 and 28 across the local bus 120. The masters 20, 22 could be the 4XX PowerPC Core central processing unit 130, the direct memory access controller 140, or the additional master 150 in FIG. 1A. The slaves 26, 28 could be the External Bus Interface Unit (EBIU) 160 or the On-chip Peripheral Bus (OPB) Bridge Unit 170. Access to the local bus 120 is granted through an arbitration mechanism 180 which is inside of the local bus 120 (also 180 in FIG. 1A) which allows masters to compete for bus ownership. Timing for all local bus signals is provided by a single clock source (not shown). This single clock source is shared by all masters and slaves attached to the local bus 120.
An important factor in the performance of the system 100 is the time required to perform a data read transfer across the local bus 120 between a master and a slave. There are three types of data read transfers: a single read, a line read (of 4, 8 or 16 words), and a burst read transfer. FIGS. 2 through 4 are timing diagrams illustrating examples of these types of data read transfers. For the purpose of these examples, assume that the master for this transfer is the master 20, and the slave is the slave 26 of FIG. 1B. Table 1 below gives the definitions of the signals illustrated on FIGS. 2 through 4.
TABLE 1 __________________________________________________________________________ SIGNAL DEFINITIONS FOR FIGS. 1B THROUGH 4 Signal Definition __________________________________________________________________________ SysClk System Clock Request (Bus Request) This signal is asserted by a master to request a data transfer across the bus. Address (Address Bus) Each master is required to provide a 32-bit address when its Request signal is asserted TQuals (Transfer Qualifiers) These signals are used to indicate to the slave the direction of the transfer, size of the transfer, and the type of transfer BE (Byte Enables) These signals are used to indicate to the slave which bytes of a word should be transfered for this access. For conventional methods of burst tranfers, this is ignored. PAValid (Primary Address Valid) This signal is asserted by the arbiter to indicate to the slaves that there is a valid address for the primary data and transfer qualifiers on the bus. SAValid (Secondary Address Valid) This signal is asserted by the arbiter to indicate to the slaves that there is a valid address for the secondary data and transfer qualifiers on the bus. AAck (Address Acknowledge) This signal indicates that the slave has acknowledged the address and will latch the address and all of the transfer qualifiers at the end of the current cycle. RdDBus (Read Data Bus) This is a 32-bit data bus which is used to transfer data during read operations from the slaves to the masters. WrDBus (Write Data Bus) This is a 32-bit data bus which is used to transfer data during write operations from the masters to the slaves. RdDAck (Read Data Acknowledge) This signal is driven by the slaves and is used for all read operations to inidicate to the master that the data is valid on the read data bus and must be latched at the end of the current cycle. WrDAck (Write Data Acknowledge) This signal is driven by the slaves and is used for all write operations to indicate to the master that the data on the write data bus is being latched at the end of the current cycle and is no longer required by the slave. RdComp (Data Read Complete) This signal is driven by the slaves and is used to indicate to the arbiter 180 that either the read operation is complete is complete or will be completed in the end of the next clock cycle. WrComp (Data Write Complete) This signal is driven by the slaves and is used to indicate to the arbiter 180 that the write operation is complete RdBurst (Read Burst) This signal is driven by the masters and is used to indicate to the slave that the read burst transfer is not complete. WrBurst (Write Burst) This signal is driven by the masters and is used to indicate to the slave that the write burst transfer is not complete. RdBTerm (Read Burst Terminate) This signal is driven by the slave and is used to indicate to the master that it should drop the RdBurst signal during the next cycle and terminate the current read burst transfer. WrBTerm (Write Burst Terminate) This signal is driven by the slave and is used to indicate to the master that it should drop the WrBurst signal during the next cycle and terminate the current write burst transfer. __________________________________________________________________________
FIG. 2 is a timing diagram illustrating an example single read transfer under conventional single read protocols. The master 20 asserts a request for a data transfer with a Request signal in cycle 1. Through the TQuals signal, the master 20 will indicate that the transfer will be a single read. The BE signals will indicate the number of bytes to be read. The data is then read and placed on the local bus 120 via the Read Data Bus (RdDBus) in cycle 3. In the meantime, the slave 26 will access the BE signals to receive information on the bytes to be read. The slave 26 will terminate the transfer by asserting the RdComp signal during cycle 2. Since by definition the Read Data Bus may be used by the slave in the cycle after the RdComp signal is asserted, the data is properly read and transferred in cycle 3. Another master may then obtain control of the local bus' Read Data Bus starting in cycle 4.
FIG. 3 is a timing diagram illustrating an example of a four-word line read transfer under conventional line read protocols. As with the single read, the master 20 asserts a request for a data transfer with a Request signal in cycle 1. Through the TQuals signal, the master 20 will indicate that the transfer will be a four-word line read. The BE signals are not used or are ignored by the slave in this case. In other words, the slave accesses the TQuals signal to receive information on the number of bytes to be read. The data is read and placed on the Read Data Bus (RdDBus) in cycles 3 through 6. The slave 26 then terminates the transfer by asserting the RdComp signal during cycle 5. The data transfer ends in cycle 6, completing the four-word line read transfer. Another master may then obtain control of the local bus=Read Data Bus starting in cycle 7.
FIG. 4 is a timing diagram illustrating an example burst transfer under a conventional burst protocol. A burst refers to a data access which comprises multiple data transfers Under the conventional burst protocol, burst transfers are open-ended, i.e. the maximum number of data transfers for the transfer is not known at the time of access offset by operating the system 100 at a higher frequency, this solution is not practical since other masters and slaves of the system may not operate on this higher frequency and thus its protocols would not be compatible with those of the system 100.
Accordingly, what is needed is a method and system for increasing the efficiency of data throughput across the local bus during burst transfers without the need to increase the frequency. This system should be compatible with existing system protocols. The present invention addresses such a need.